An EDS Outline for the First Proof-of-Principle Prototype

Regarding the writing of a formal EDS, I have templates in Microsoft Word that I use for creating such documentation. But since I’m working for myself and not some medical device company, where the FDA is always looking over your shoulder, I will just stick to writing outlines rather than full formal documentation.

The meta-goal of this project will be the creation of an ASIC level asynchronous array of simple processors. (Yes, I know that sounds a bit ambitious, but it doesn't cost anything to dream.) While that level of hardware creation might be beyond my resources, there are two layers of hardware creation that are still accessible to me and my pocketbook. The first layer will be the creation of a simple proof-of-principle prototype board, while the second layer will be the creation of a larger 8 x 8 asynchronous array.

So this blog post will restrict itself to an EDS outline for that first layer proof-of-principle prototype. The IDS for this project was already outlined in a past blog post, so this post will just concentrate on outlining the EDS side of the design specifications.

As a hobbyist my primary design constraint is budget. Building a larger 8 x 8 asynchronous array will be an expensive out of pocket undertaking. So before I undertake such an expensive hardware design project, I want to be completely confident that the hardware will work and do what I want it to do, so one of the functions of this proof-of-principle prototype will be to validate the functionality of the various pieces of the final project.

So what are the aspects of the final design that I want to validate using this reduced complexity prototype? In no particular order...

• Daisy chain programming via the JTAG interface. 
• Programming environment. 
• Ring oscillator design. 
• Clock speeds attainable. 
• Machine code command structure. 
• Run-time debug environment. 
• Will the chosen FPGA parts be adequate for their expected functionality? 
• Power supply questions about current draw during operation. 

In other words, this first level of hardware design is for the validation of what will become the basic processor cell that will tiled into a larger asynchronous array. So validation of this first proof-of-principle prototype needs to be against whatever applications that a full sized ASIC level asynchronous array of simple processors would be running. But I don’t know what that is yet so this EDS outline will have remain a work in progress for now.