Monday, February 16, 2015

Proposed Proof-of-Principle Board Design

The final design goal I have in mind is to reproduce the asynchronous processor array structure of the GA144 chip on a PCB size scale using FPGA parts as the individual cell elements. The most natural structure for such a design would be an 8 x 8 array of processors. But a project like this could easily cost up to about $2000. That’s more money than I can afford to spend on just an experiment. So before I walked down that pathway, I want to do a small proof-of-principle prototype to confirm that my hardware design ideas will work on the larger scale.

A proof-of-principle prototype needs to be quick, simple, and, while reduced in size, still retain enough functionality to be able to verify the design ideas for the full-sized end design. At this level, a number of design constraints come into play.

First is the allowed board size. I work through Sunstone Circuits for my PC board fabrication needs. Their pricing structure for four layer PCB's works out so that for boards 10-in² or less, the price is half of the next size up. Since cost is a hard constraint for this project, this sets my board size to 10-in² or less. Sunstone also has a minimum order of two boards. So if I am clever and layout a single board in a symmetric fashion, I can take the second board and attach it to the first, end-to-end, and effectively have a 20-in² PCB. I’ve already tried this trick in my PCB layout tools, and it works great.

Second, the choice for the FPGA part is pretty straightforward for me. The last few years I’ve been working exclusively with FPGA parts from Lattice Semiconductor. Since I have all the software and programming tools in place for Lattice parts, this is the natural choice for me.

Since I’m going to hand-solder these parts, any kind of ball grid package is off the table as a design choice. This leaves the leaded TQFP parts as my only option.

In terms of logical complexity, my goal is to create individual cells in my asynchronous array which are complete stack-based processors with sufficient memory to be able to run more than simple routines. Also, having DSP functionality in my FPGA part would allow it to work as a neural network element.

Third, since an 8 x 8 array will be a total of 64 processors, cost will be a critical consideration. Adding all of these constraints together and going through Lattice Semiconductor’s product offerings, there is one part that stands out; that is the ECP2 family of processors, with the particular part choice being the LFE2-6E-5T144C

Fourth is the design of a ring oscillator. This turned out to be not as straightforward as I thought going into this project. This is a subject which I think will deserve a separate blog post. But for now, the choice seems to have come down to an active delay line as the timing source for my oscillator.

And lastly, there is the question of how to get data and updated program code into and out of the array. While I do have a UART written in Verilog that I can port to one of the FPGA parts, I’ve chosen to leave that out of the array elements and tack on an eight-bit PIC processor from Microchip. The whole idea is to do this proof-of-principle project as quickly as possible. So even though adding an extra processor to the array design might seem like extra work, it isn’t. The reason why is that I’ve been doing design work for the PIC processors for years, and I have a lot of source code as well as schematics and test software written in LabVIEW already that I can immediately make use of.

So this is where the design is: a single board, of approximately 9.5-in², that will contain two FPGA parts and one PIC18 part, along with RS-232 drivers and a 1.2 volt power supply for the FPGAs. One board laid out in a symmetric fashion like this can be rotated and soldered to itself to form a 2 x 2 array of FPGAs with PIC processors on diagonal corners. As work goes, I will post the schematics, part lists and artwork Gerber files on my regular website,

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